The present invention relates to a semiconductor integrated-circuit device employing a silicon on insulator (SOI) substrate, and to an art for preventing a malfunction and a variation of an operating speed from occurring due to fluctuations of potentials at a power line and a ground line with a simple structure without an increase in area, and for further improving heat dissipation efficiency.
Semiconductor integrated-circuit devices including a bulk MOS device and SOI device are already known. Above all, the SOI device is a semiconductor integrated-circuit device having an SOI structure in which a p-channel MOS transistor and an n-channel MOS transistor are formed in a semiconductor layer formed on a p-type or an n-type semiconductor substrate with an embedding insulating layer (hereinafter, referred to as related art 1).
In the SOI type semiconductor integrated-circuit device according to related art 1, especially, the p-channel MOS transistor and n-channel MOS transistor are connected to a power line, a ground line, and a signal line and have the capability of an inverter circuit.
The SOI type semiconductor integrated-circuit device according to related art 1 gains an advantage over the conventional bulk CMOS device from the viewpoint that since the capacitance of a diffused layer can be made smaller, the time required for charging the signal line gets shorter accordingly and the operating speed gets higher. However, the capacitance of the diffused layer to be exerted between the power line and the ground line also gets smaller.
In general, in semiconductor integrated-circuit devices, when a large current flows at a time, for example, when an output buffer is driven, the potentials at a power line and a ground line readily fluctuate due to the impedances of lead wires and bonding wires.
However, normally, in the conventional bulk CMOS device, a power line is also used to apply a voltage to an n-type well, and a ground line is also used to apply a voltage to a p-type well. The large capacitances of the wells work between the power line and ground line. The capacitances realize a bypass capacitor. In the bulk CMOS semiconductor integrated-circuit device, therefore, variations of potentials at the power line and ground line caused by a noise occurring during operation can be suppressed.
By contrast, in the SOI type semiconductor integrated-circuit device according to related art 1, a low-capacitance diffused layer is connected to the power line and the ground line. When the device is in operation, a supply potential and a ground potential are likely to vary for the structural reason. An event that the supply potential and the ground potential fluctuate is equivalent to an event that the supply voltage for the circuit varies transiently during the operation of the circuit. The operating speed of the circuit, therefore, varies greatly. At worst, the circuit may malfunction. In some SOI type semiconductor integrated-circuit devices, therefore, a ground line and semiconductor substrate are interconnected in order to fix the potential at the semiconductor substrate to the ground potential. Even in this case, the potential at a power line is liable to vary.
For solving the foregoing problem, an SOI type semiconductor integrated-circuit device has been proposed in Japanese Unexamined Patent Publication No. 3-222361 (hereinafter, referred to as related art 2). In the semiconductor integrated-circuit device according to related art 2, a p-channel MOS transistor and an n-channel MOS transistor are formed in a semiconductor layer formed on a semiconductor substrate with an embedded insulating layer. According to related art 2, the p-channel transistor is connected to a signal line and has the capability of an inverter circuit. A power line and a ground line are connected to two electrodes formed in the, embedded insulating layer, lying immediately below the transistors. The two electrodes are shaped like flat plates, and opposed mutually with a given space between them, thus realizing a capacitor. Owing to this structure, a large capacitance is exerted between the power line and ground line. Consequently, fluctuations of potentials at the power line and the ground line occurring during operation of the integrated circuit can be suppressed.
However, related art 2 has not revealed a method of creating electrodes in an embedded insulating layer. The insulating layer and the flat plate-like electrodes are layered alternately, and a monocrystalline semiconductor layer is formed on both of the insulating layer and the flat plate-like electrodes. This presumably leads to a drawback that the manufacturing process gets very complex and the manufacturing cost gets very high.
Moreover, related arts 1 and 2 as well as MOS semiconductor circuits have a problem that electrical characteristics, especially mobility, deteriorate because of heat dissipated during operation of transistors. For example, an on-state current decreases.
In particular, as far as the SOI device in accordance with related art 1 is concerned, the heat conductivity of the insulating layer, embedded insulating layer, immediately under the transistors is often so low that heat dissipation to the semiconductor substrate is achieved imperfectly. In other words, since the power line, the ground line, and the signal line are connected to the transistors, part of heat dissipated by the transistors is exhausted to a wiring. However, since the heat capacity of the wiring is small, heat dissipation is achieved imperfectly. Heat generated by the transistors is accumulated. The temperatures of the transistors rise during operation thereof. Consequently, the electrical characteristics of the MOS transistors deteriorate.